POET’s Breakthrough Leap to End Moore’s Law Limits

Posted: September 11, 2014 in Technology News
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Dr. Geoff Taylor writing ebeam gate features on a POET wafer

Dr. Geoff Taylor writing ebeam gate features on a POET wafer

Toronto, Ont., Canada — An exciting new technology leap in semiconductor chip design based on a combination of optics and GaAs promises to change integrated circuits drastically, making them up to 10X to 100X faster than conventional silicon while reducing power consumption 80% — making the development very eco-friendly. Prototypes will be ready for display and testing with third parties by the end of 2014.

The new development comes from POET Technologies (TSX: PTK and OTCQX: POETF), a publicly listed Company and the developer of the “POET” Platform. POET’s head office is in Toronto, ON, Canada, and its research and development lab is in Storrs, CT. POET designs III-V semiconductor devices for military, industrial and commercial applications, including infrared sensor arrays and ultra-low-power random access memory. POET Technologies has several patents issued and pending for the POET process, with potential high speed and power-efficient applications in devices such as servers, tablet computers and smartphones. It has been the company’s mission to provide a valid solution to the ageing designs used in traditional silicon CMOS.

The Company’s name is an acronym for “Planar Opto-Electronic Technology”, a revolutionary III-V process used to monolithically build electrical, optical, and electro-optical integrated circuits. POET supports a full range of electrical and optical active and passive circuit components. POET-based devices have the potential to provide very high performance vs. existing silicon-based devices (up to 100X faster) with very low power consumption, up to 80 percent less than existing silicon devices. The POET process is much more versatile than legacy hybridized fabrication of compound semiconductor devices (GaAs, InP, others) and can be implemented using existing CMOS chip-making equipment.

POET will be fully compatible with existing semiconductor design and manufacturing flows, allowing unprecedented integration of functions that take multiple chipsets today into a single chip for large component cost reduction, and — particularly for optics — tremendous (~80 percent) reduction in assembly and test costs.

This breakthrough has been achieved by turning to strained InGaAs quantum wells with indium concentrations of 70 percent or more; mobility and channel velocity increases, and operation of the circuit at 0.3 V, should enable up to a ten-fold gain in performance and up to 80 percent lower power requirements compared to a silicon-based CMOS IC.

18 Years of R&D
Development of this technology started in the early 1990s in the labs at the University of Connecticut. Since then, more than 18 years have been devoted to developing and proving out numerous components of the platform by POET’s Chief Scientific Officer and Director Dr. Geoff Taylor and his team. POET’s business model is to license the III-V semiconductor process technology IP to customers and foundry partners to enable designs, to produce devices that include analog, digital and optical functions on the same die for a variety of markets including, but not limited to, hand-held smartphones and tablets, PCs, servers, data centers, military and industrial applications.

With this technology, the compatibility issue between transistors and the optical devices disappears, and it is possible to form high mobility channels for both the n-type and p-type transistors. One challenge had been the assumption that these high-mobility materials have to be introduced on a silicon substrate. In our case, we use substrates made of GaAs. These are currently available in diameters up to 200mm, and there is no fundamental barrier to the production of 300mm equivalents which is a commercial foundry standard. Our preferred growth technique for depositing III-V layers on this foundation is molecular beam epitaxy (MBE), and this can be applied to substrates of this size. Tier 1 fabs already use this approach to deposit material on 300mm wafers, so the only barrier to a switch of substrate is cost, not availability of the technology. Differences between the price of silicon and GaAs substrates will shrink as shipments of the latter rise, and costs could be further reduced through innovations in substrate release techniques. The POET fabrication process employs most of the same set of foundry tools currently used for silicon CMOS, so minimal reconfiguration is required.

The idea of using GaAs rather than silicon to make digital circuits is not new. During the nMOS era that spanned the 1970s and early 1980s, GaAs MESFET technology was a contender for silicon E/D logic applications. And later, during the development of CMOS, the GaAs HEMT was also considered for high-speed logic circuits.

The key differences to the present technology are that we are now able to integrate both electronic GaAs devices with optical GaAs devices, and we have substituted optical interconnect to eliminate long metal interconnects.

Furthermore, in contrast to other technologies that are trying to go beyond the silicon CMOS barriers, the POET approach uses conventional fab processes to produce its devices together with MBE wafers, the only epitaxial technique to provide precision doping, thickness control and laser quality.

A significant capability of the technology is that the epitaxial process is unmatched in its ability to realize self-assembled quantum dots. Although not a current objective, it turns out that the modulation-doped interface formed with this technology, which is a normally off channel, is ideal for the implementation of the single-electron transistor. This form of transistor can access engineered quantum dots at the interface, which have quantum levels differentiated by spin. It is possible that these single-electron transistors could aid the development of quantum computing, with electron spin providing the quantum variable to form quantum computing logic blocks.

Moore’s Law Revoked
For almost 50 years, Moore’s Law has dictated the pace of technological change. As the number of transistors on a chip double approximately every 1.5 to 2 years, this increases the performance capabilities of computing devices and the many functions they make possible. Unfortunately, with present silicon-based integrated circuits and manufacturing processes, performance and cost improvements under Moore’s Law are increasingly unsustainable, and will soon come to an end.

These physical limitations will increasingly impede electronics manufacturers from continuing to build smarter, faster, more efficient and cheaper devices — including sensors, lasers and computing devices.

By integrating optics and electronics onto one monolithic chip, POET expects to provide its customers with new direction that is no longer strait-jacketed by the limitations of silicon technology.

See also Compound Semiconductor’s magazine (June 2014, page 52-57). The digital edition can be found directly on Compound Semi’s digital edition page here: http://www.compoundsemiconductor.net/csc/magazine.php.


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